There have been demanded ferroelectric non-volatile memories in which operation speed and the number of data rewriting are improved by utilizing spontaneous polarization characteristics of ferroelectric materials as compared with conventional non-volatile memories such as EEPROM and flash memory. Memory cell structures fundamental to the non-volatile memories are classified into the following two types.
A first type is a type wherein a conventional memory capacitor of DRAM is replaced with a ferroelectric capacitor. The first type includes a structure wherein a ferroelectric capacitor of a ferroelectric thin film sandwiched with electrodes is connected to a source or a drain of a MOS transistor through a polysilicon plug or the like. This is called a one transistor-one capacitor type memory cell. Currently, ferroelectric non-volatile memories utilizing the memory cell of the first type have been practically used.
However, to deal with an increase of memory capacity and higher integration for the future, realization of a structure in which one transistor solely constitutes a memory cell (hereinafter this structure is referred to as a second type) has been demanded. However, since there are problems in that ferroelectric materials having necessary characteristics for the realization have not been obtained and fabrication techniques thereof have not been established, memory cells of the second type have not been materialized yet. Hereinafter, the problems are explained in detail.
The memory cell of the second type utilizes, as its fundamental structure, a gate element of MFS (ferroelectric material--metal--semiconductor) structure wherein a ferroelectric thin film and a gate electrode are layered on a surface of a semiconductor substrate. Most of the ferroelectric thin films currently applicable are oxides and require a thermal treatment at a high temperature in an oxidizing atmosphere to crystallize the oxides at the formation of the thin films. Therefore, at the formation of the ferroelectric thin film, an oxide layer (e.g., SiO.sub.2 layer) having low dielectric constant tends to be formed at its interface to the semiconductor substrate (e.g., Si). Further, it is problematic in that reaction and mutual diffusion between elements constituting the ferroelectric thin film and the semiconductor substrate cannot be avoided.
Accordingly, it is also difficult to obtain normal characteristics of the MFS because it is extremely difficult to realize a favorable interface state. That is, moving carriers are generated owing to impurities and defects introduced to the inside of the semiconductor substrate or the interface, which leads to a flat band shift in C-V hysteresis characteristics of the MFS and an increase in leak current. As a result, the C-V hysteresis characteristics which reflect the characteristics of the ferroelectric material are lost in a short period so that the memory cannot be maintained. Thus, even if an FET is actually fabricated in the conventional MFS structure, a memory maintaining time is only a few minutes to a few hours. In contrast, the memory cell of the first type realizes a memory maintaining time for more than 10 years. The most important subject of the memory cell of the second type for practical use thereof is an improvement of the memory maintaining time.
Ferroelectric materials used for the memory cell of the second type are desirably materials which are capable of reversing polarization at a low voltage (low coercive electric field Ec) and do not deteriorate (are not exhausted) in the ferroelectric characteristics through repetition of polarization reversal. Further, for forming directly on the Si substrate, a ferroelectric material capable of forming at a temperature as low as possible and a fabrication process thereof are required to inhibit the reaction and mutual diffusion between the elements.
As the ferroelectric materials used for the memory cell of the second type, ferroelectric materials made of Bi-containing oxide of layered structure are excellent in resistance to exhaustion and expected as an alternative to conventional Pb-containing ferroelectric materials represented PZT. Among them, a ferroelectric material Bi.sub.4 Ti.sub.3 O.sub.12 having great anisotropy exhibits good bulk characteristics of spontaneous polarization Ps=50 .mu.C/cm.sup.2 and Ec=50 kv/cm in the direction of a-axis, and Ps=4 .mu.C/cm.sup.2 and Ec=5 kv/cm in the direction of c-axis.
The ferroelectric material exhibiting smaller coercive electric field in the c-axis direction is useful for the memory cell of the second type, and therefore it has been proposed in the past to apply the material to the MFS structure (for example, see IEEE Trans. Electron Devices, ED-21 (1974) 499-504; J. Appl. Phys. 46 (1975) 2877-2881). These documents describe a process for obtaining a crystalline thin film by sputtering at a high temperature such as 675.degree. C. or more and a process for obtaining a crystalline thin film by annealing at 650.degree. C. after formation by sputtering at a low temperature.
However, in the above processes, since the thin film is formed al a high temperature, a layer having low dielectric constant made of silicon oxide is generated at the interface between the Si substrate and the ferroelectric thin film. When a voltage is applied to the resulting memory cell of the MFS structure, a major part of the applied voltage is distributed to the low dielectric layer. Accordingly, it is difficult to apply enough voltage to the ferroelectric thin film having higher dielectric constant for the reversal of the polarization. Further, the ferroelectric thin film is not sufficient in an orientation along the c-axis direction and the thickness thereof is as great as 1 .mu.m or more. Therefore it requires a high voltage to be applied to reverse the polarization of the ferroelectric thin film. Moreover, it is difficult to perform a stable memory operation because of an electric charge injection phenomenon caused by defects generated by the reaction at the interface between the Si substrate and the ferroelectric thin film.
Then, in order to realize a more favorable connection at the interface between the ferroelectric thin film and the semiconductor substrate, there has been studied a MFIS (metal ferroelectric material--insulator--semiconductor) structure in which the ferroelectric thin film is formed on an insulating film formed preliminary by epitaxially growing an insulating material having relatively high dielectric constant into a thin film on a surface of the Si substrate. As the insulating film, an epitaxial film such as ZrO.sub.2 or CeO.sub.2 is used. The insulating film is generally formed by a vapor deposition technique and requires a thermal treatment at a temperature as high as 800.degree. C. or more. Therefore, in a memory cell of the MFIS structure utilizing CeO.sub.2 as the insulating film and PbTiO.sub.3 as the ferroelectric thin film (for example, see Jpn. J. Appl. Phys. 34 (1995), 4163-4166), an SiO.sub.2 layer is generated between the Si substrate and the insulating film. Further, the C-V hysteresis characteristics are deteriorated over about 11 hours. Moreover, since the insulating film and the ferroelectric film are made of completely different materials, they need to be formed individually with different forming devices, which makes the process complicated.
To solve the above problems, the inventors of the present invention have reported a process for forming a bismuth silicate film as the insulating film on the surface of the Si substrate and forming thereon a ferroelectric thin film made of Bi.sub.4 Ti.sub.3 O.sub.2 oriented along the c-axis direction (see Japanese Unexamined Patent Publication No. HEI 8(1996)-12494).
In the above process, a SiO.sub.2 layer is removed first from the surface of the Si substrate. Then, a thin film of bismuth silicate (Bi.sub.2 SiO.sub.5, Bi.sub.12 SiO.sub.20 and the like) is formed by a metal-organic chemical vapor deposition (MOCVD) technique. That is, the bismuth silicate film is formed by supplying a Bi material gas and an O.sub.2 gas simultaneously to the surface of the Si substrate and reacting Si on the surface of the Si substrate with Bi and O in the material gases. Then, a thin film of Bi.sub.4 Ti.sub.3 O.sub.12 is formed on the bismuth silicate film by adding a Ti material gas.
In this process, elements for constituting the insulating film are all contained in elements constituting the Si substrate and the ferroelectric thin film. Therefore it is advantageous in that mixing of impurity elements is avoided and the insulating film and the ferroelectric thin film can be successively formed in the same forming device.
Incidentally, processes described in Jpn. J. Appl. Phys. 32 (1993), 135-138 and Japanese Unexamined Patent Publication No. HEI 5(1993)-243525 are known as processes for forming the thin film of Bi.sub.4 Si.sub.3 O.sub.12, for example. That is, the SiO.sub.2 layer is preliminarily formed on the surface of the Si substrate. On the SiO.sub.2 layer the Bi.sub.4 Si.sub.3 O.sub.12 thin film is formed by supplying the Bi material gas and the O.sub.2 gas simultaneously to the surface of the SiO.sub.2 layer by the MOCVD technique.
A surface morphology of the ferroelectric film formed by the above process is made of crystalline particles having a plate form. Therefore unevenness and pinholes are present on the surface. Accordingly, the thickness of the film may be locally insufficient because of the unevenness on the surface, and favorable ferroelectric characteristics arc hardly obtained with the thickness as small as 200 nm or less because of the pinholes. Further, in terms of reduction of a driving voltage of a semiconductor device, the thickness of the ferroelectric thin film is required to be reduced in the MFIS structure, for which the ferroelectric thin film needs to be formed more accurately.
Furthermore, it is necessary to add the Ti material gas while forming the Bi.sub.4 Ti.sub.3 O.sub.2 thin film after the bismuth silicate film is formed. According to this, a modification of other forming conditions (flow rate of a carrier gas and the like) is required, which makes the formation process complicated.
Additionally, in order to obtain a memory cell of the MFIS structure with a longer memory maintaining time by inhibiting the mutual diffusion and the like between the semiconductor substrate and the bismuth silicate film and preventing deterioration of the state of the interface therebetween, it has been demanded to lower the temperature for forming the bismuth silicate film (550.degree. C. or more in the case of Bi.sub.2 SiO.sub.5, for example) to a further extent.